Codasip joins OpenHW® Group to contribute to RISC-V verification

Munich, Germany, September 21, 2022 – Codasip, the leader in customizable RISC-V processor IP, announced it has joined OpenHW Group. Together with the existing OpenHW ecosystem, Codasip will contribute to the development of standards across various techniques including formal verification. Codasip will contribute supporting IP, tools, and methodologies to help the wider community benefit from its experience in the development of high-quality, standard and customized RISC-V cores.

OpenHW Group transforms the development of microprocessor technology and related sub-systems peripherals through a collaborative, distributed engineering, open-source ecosystem. A non-profit global organization driven by its members and individual contributors, OpenHW enables hardware and software designers to collaborate in the development of open-source cores, IP, tools and software. OpenHW provides an infrastructure for hosting high-quality open-source hardware developments in line with industry best practices.

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Codasip is heavily committed to processor verification as a fundamental part of designing processor cores and is pushing for the establishment of agreed strategies and standards to ensure the quality of RISC-V cores continues to improve. OpenHW Group is an active member of RISC-V International with a shared belief in the importance and prioritization of commercial-grade verification for RISC-V.

Rick O’Connor, President and CEO of OpenHW Group, commented, “I am excited to welcome Codasip as a strong addition to OpenHW Group. The OpenHW ecosystem provides an infrastructure for hosting high-quality open-source HW developments in line with industry best practices. Codasip puts significant emphasis on the importance of processor verification for RISC-V. As a leader in RISC-V processors, Codasip’s role will be crucial in setting industry standards and collaborating on projects with the 90+ members of OpenHW Group.”

Mike Eftimakis, Codasip VP Strategy and Ecosystem, added, “In the strong and growing RISC-V community, everyone supporting the open standard benefits us all. We see the roles of open-source IP and commercial IP as complementary and though we sell our cores, we also see open source as a critical part of the ecosystem and for the success of RISC-V. We acknowledge the importance of OpenHW Group’s goals of providing wider access to high-quality cores and will work towards these goals by sharing our expertise in verification but potentially also in other areas where we see a need to step up efforts for the shared benefit of the processor industry.”

Edward Wilford, Senior Principal Analyst, IoT Hardware at Omdia said: “There is no question that a set of transparent, consistent and meaningful standards could go a long way towards improving the overall level of quality expected in the industry. It is crucial that ‘open source’ doesn’t in any way come to signify ‘anything goes’, especially with the increasing attention vendors, manufacturers and consumers are paying to chip and device security. It’s fair to say an SoC, a network, or a sensor array is only as secure and as capable as its weakest element, so any initiative that adds trust to the ecosystem, whether commercial or open-source, should be welcomed.”

About Codasip
Codasip delivers leading-edge RISC-V processor IP and high-level processor design tools, providing IC designers with all the advantages of the RISC-V open ISA, along with the unique ability to customize the processor IP. As a founding member of RISC-V International and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded and application processors. Formed in 2014 and headquartered in Munich, Germany, Codasip currently has R&D centers in Europe and sales representatives worldwide. For more information about our products and services, visit www.codasip.com. For more information about RISC-V, visit www.riscv.org.

About OpenHW and CORE-V
The charter of the OpenHW Group is to serve developers of processor cores and hardware and software engineers who design SoCs with greater awareness, understanding and availability of open-source processor implementations for use in high volume production. The OpenHW Cores Task Group has the mandate to develop the roadmap and related open-source IP for the cores the CORE-V Family of open-source RISC-V processors.

The OpenHW Verification Task Group has the mandate to develop best-in-class verification testbench environments for the CORE-V Family of cores and IP blocks designed by the members of the OpenHW Group. For more information on the OpenHW Group and task group projects visit: www.openhwgroup.org.

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